The present invention relates to a semiconductor memory device and a manufacturing method for semiconductor memory device. For more details, the present invention relates to a semiconductor memory device composed of a field effect transistor having function to transfer a change of electrical charge to a change of current, and a manufacturing method for the semiconductor memory device thereof.
Conventionally, the nonvolatile semiconductor memory device fabricated by the MOSFET having the charge storage layer is commonly known. In the above semiconductor memory device, the digital bit information is stored by charging an electrical charge into the charge storage layer through the insulation film and the information is read out based on the change of conductance of the MOSFET corresponding to the change of electrical charge thereof. For example, the MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type semiconductor memory device is fabricated by the MOSFET using the silicon nitride film thereof as the charge storage layer and is researched more actively from the possibility for low-voltage writing information or low-voltage erasing information than the semiconductor device using floating gates formed by poly silicon.
In the patent document 1 and 2, there is a description of the NOMOS type semiconductor memory device fabricated by the MOSFET having the electrical charging function in the gate insulation film. The above semiconductor memory device includes the semiconductor substrate having the source region and the drain region, the gate insulation film formed by the multi-layer structure between the source region and the drain region on the semiconductor substrate, and the gate electrode formed on the gate insulation film. The above insulation film has the structure, generally referred to as “ONO (Oxide Nitride Oxide)” structure, having the sandwiched silicon nitride film by the first silicon oxide film and the second silicon oxide film. In the semiconductor memory device having the above structure, the digital bit information is stored as follows. The electrical charge is put from the channel layer formed between the source region and the drain region into the silicon nitride film through the first silicon oxide film by adjusting voltage of the gate electrode, the source region, the drain region, and the semiconductor substrate, and the electrical charge being put thereto is stored in the trap energy level generated in the interface between the silicon nitride film and the first silicon oxide film or in the silicon nitride film.
Additionally, in the patent document 3, there is a description of the semiconductor memory device forming the bar of charge storage part along the direction of the gate width independently from the both side walls of the gate insulation film of the MOSFET. The above semiconductor memory device includes the semiconductor substrate having the source region and the drain region, the gate insulation film and the gate electrode formed on the semiconductor substrate, and the bar of charge storage part placed in the side of the gate insulation film. The charge storage part consists of the bar of carbonaceous matter film formed as the charge storage layer and the tube of insulator surrounding the carbonaceous matter thereof. In the above semiconductor memory device, the digital bit information is stored as follows The electrical charge is put from the channel layer formed between the source region and the drain region into the carbonaceous matter through the first silicon oxide film by adjusting voltage of the gate electrode, the source region, the drain region, and the semiconductor substrate, and then the electrical charge being put thereto is confined in the trap energy level generated in the interface between the carbonaceous matter and insulator or in the carbonaceous matter. The object of the above semiconductor is reducing the thickness of the gate insulation film without losing enough memory function by separating the charge storage part from the gate insulation film and by separating memory function of the charge storage part from transistor function of the gate insulation film.    [Patent document 1] Patent description of U.S. Pat. No. 6,137,718    [Patent document 2] Patent description of U.S. Pat. No. 6,049,995    [Patent document 3] Japanese Patent Journal No. 2004-335595